TFTs are used in devices such as LCD display panels. A TFT comprises a channel in the form of a thin film of semi-conductor material in a channel area on a substrate and a conductive gate, separated from the semi-conductor material by an insulating layer. A top gate or a bottom gate may be used, wherein the semi-conductor material is between the gate and the substrate or the gate is between the semi-conductor material and the substrate respectively. The gate crosses the channel area, defining source and drain areas in the channel area on either side of the gate.
U.S. Pat. No. 7,341,893 describes a method of manufacturing a device with such transistors by means of imprinting, called the SAIL process (self-aligned imprint lithography). In the SAIL process, a single resist layer of variable height is used to define different areas on the substrate that will be processed using different process steps. The resist is made to have different height levels above the different areas by means of stamping, or a gray level photo exposure pattern.
The principle is that the resist is etched in successive steps, each for a duration that removes the resist from its lowest (remaining) height level to the bottom of the resist, without fully removing the resist where it has a higher height level. Subsequently, a process step can be applied to the exposed areas through the mask formed by the remaining resist. This can be repeated for successively higher levels. The SAIL process has the advantage that the relative position of all the areas is defined by the 3D pattern of a single resist layer. No alignment of different patterning steps of different resist layers is needed.
Underneath the resist a stack of a plurality of thin film layers for use to form transistors is provided. This may include a layer of semi-conductor material, a (gate) isolation layer, a metal layer etc. The different process steps after removal of the resist from respective height levels may provide for removal of part or all of the layers in the stack through the mask formed by the resist after etching from the respective height level and/or deposition of additional material through that mask.
U.S. Pat. No. 7,341,893 describes an application of a SAIL process to the manufacture of a bottom gate TFT. In this process, a stack of thin film layers is provided on top of a substrate with parallel conductive strips. The gate electrodes are formed by sections of a plurality of such parallel strips. The channel runs from the source to the drain separation transverse to the long direction of the strips. The stack of thin film layers contains a gate insulation layer, a semi-conductor layer and a top metal layer. In the SAIL process different height levels are use to etch the strips where needed to isolate sections that form the gate electrode, to deposit gate contacts, isolate different channels and to remove top metal in order to separate source and drain contacts. Because the semi-conductor layer overlies the gate electrode it is easy to etch the channel in the semi-conductor layer so that the gate electrode extends beyond it, preventing source-drain leakage around the gate.
When applied to a top gate TFT, it is more difficult to avoid this type of leakage in a SAIL process. In a multi-mask process (not SAIL), the semi-conductor layer can be patterned using a first mask before the gate electrode layer is deposited and defined using a second mask, the masks ensuring that that the gate electrode extends beyond it. The problem with the SAIL process is that the gate electrode lies over the semi-conductor layer, so that the semi-conductor layer must be etched while the gate electrode lies on top of it. It is known to use an undercutting etch process to remove the semi-conductor layer also under the edge of the gate electrode, where it could otherwise give rise to source-drain leakage around the gate. Another solution is to extend the gate electrode well beyond the source-drain areas, thereby forcing any leakage current to make a large detour that increases resistance in the leakage path.